Extended bandwidth digital doherty transmitter

专利摘要:
An extended bandwidth digital Doherty transmitter includes a baseband signal processing block including a digital predistortion unit. It also includes a digital signal distribution unit and a digital phase alignment unit, a signal up-conversion block, an RF power amplification block including the carrier amplifier and one or two peaking amplifiers; and an RF Doherty combining network. In another aspect, a digital Doherty transmitter includes a baseband signal block including a digital predistortion unit, a digital signal distribution unit and an adaptive digital phase alignment unit. In this aspect a signal up-conversion block includes three digital-to-analog converters (DACs) and a tri-channel up-converter or three single-channel up-converters. There is also an RF power amplification block including the carrier amplifier and two peaking amplifiers, and an RF Doherty combining network which includes quarter wavelength impedance transformers.
公开号:SE1550180A1
申请号:SE1550180
申请日:2013-07-31
公开日:2015-02-18
发明作者:Fadhel Ghannouchi；Ramzi Darraji
申请人:Ramzi Darraji；Fadhel Ghannouchi；
IPC主号:

专利说明:

[1] [0001]The present invention relates generally to digital Doherty transmitters, and, more P' icularly to an extended bandwidth digital Doherty transmitter.
[2] [0002]To cope with the ever-increasing number of wireless networks users, modern wireless communication standards (3rd generation and beyond) employ spectrum efficient modulation and access techniques, such as quadratic amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM) and code division multiple access (CDMA). Although these techniques permit an efficient management of the overcrowded radio frequency (RE) spectrum, they also result in creating highly varying envelope signals that are characterized with high peak-to-average power ratio (PAPR). To avoid signal clipping and loss of transmitted information through distortion during power amplification, the transmitter should handle the peak values of the transmitted signal even though it mostly operates at significantly lower average power levels. Accordingly, the power amplifier (PA) of wireless transmitter is forced to operate at large back-off from its saturation point where the power efficiency of the PA drops drastically.
[3] [0003]A popular power amplification architecture for enhancing the efficiency at backed-off output power region is the Doherty amplifier architecture. Fundamentally, a Doherty' amplifier is composed on 1) one main amplifier (commonly denoted as carrier amplifier) that is PCT/CA2013/000678 operating in class-AB and performing signal amplification for all input signal levels, 2) at least one auxiliary amplifier (commonly denoted as peaking amplifier) that is operating in class-C and performing signal amplification starting from a predefined signal level, 3) an input analog power divider for splitting the input signal between the carrier amplifier and the peaking amplifier(s). 4) a non-isolated Doherty output power combiner for combining the outputs of the carrier amplifier and the peaking amplifier(s) which includes quarter wavelength transformers, and 5) 50 Ohms lines inserted at the input of the peaking amplifiers andior carrier amplifier to balance the delay between the branches of the Doherty amplifier_ The use of a non-isolated power combiner initiates an active load modulation mechanism that is based on dynamically changing the load presented to the carrier amplifier through the impedance modulation triggered by the peaking amplifier(s). This allows the carrier amplifier to operate efficiently until it reaches its optimal load while the peaking amplifier(s) is/are simultaneously contributing to the output power of the Doherty amplifier. 100041Practically, the two-stage Doherty amplifier which consists of one carrier amplifier and one peaking amplifier; and, the three-stage Doherty amplifier which consists of one carrier amplifier and two peaking amplifiers are the most used architectures in Doherty based RF transmitters. Practical implantations of four-stage and higher order-stage Doherty amplifiers are rare and not fully convincing in their performance. The main reasons are the rather complex design and the excessive costs of implementation for no significant performance improvement as compared to the two or three-stage Doherty amplifier architecture.
[5] [0005]Ideally, two-stag (three-stage) Doherty amplifier has two (three) maximum efficiency points located within a range of up-to 6 dB (12 dB) of output power back-off PCT/CA201.3/000679 relatively to the saturation output power point. This feature makes the two-stage and three-stage Doherty amplifiers the most suitable architectures for power amplification in 3rd generation and beyond wireless communications applications where the PAPR of the modulated signals is typically ranging between 6 and 12 dB. In practice, two-stage Doherty amplifiers are more suitable when the PAPR is about or slightly higher than 6 dB and three-stage Doherty amplifiers when the PAPR of the signal is significantly higher that than 6 dB. The achievet of such a superior performance requires a quasi-perfect load modulation mechanism which is not likely to happen in fully-analog implementations due to limitations related to inherent hardware impairments in the RF blocks of two-stage or three-stage Doherty amplifiers. [00061In the case of two-or three-stage Doherty amplifier, the dissimilarity in class of operation of the carrier amplifier and the one or two peaking amplifiers results in complex gain fluctuation between the output branches of the Doherty amplifier. As a result, the output signal amplitude from the carrier amplifier and the output signal amplitudes from peaking amplifiers do not match with the ideal current profiles governing the correct operation of the Doherty amplifier. This translates into an imperfect load modulation mechanism and degraded efficiency. 100071In a number of device (transistor) technologies (such as high electron-mobility transistor (I1EIVIT) and gallium nitride (GaN), etc.), the difference in bias conditions between the carrier amplifier and peaking amplifiers results in power-dependant and highly nonlinear phase misalignment within the output branches of the Doherty amplifier which causes severe output power loss, deficient load modulation and degraded efficiency. 100081Another problem related to the Doherty PA is the narrow bandwidth performance.
[10] [0010]In the description of the invention, a three-stage Doherty amplifier will be used.
[15] [0015] Figure 2 is one embodiment illustrating a detailed block diagram of the architecture of Figure 1, using a single tri-channel up-converter. 100161 Figure 3 is an alternate embodiment illustrating a detailed block diagram of the architecture of Figure 1, using three single channel up-converters.
[17] [0017] Figure 4 is an example of a possible signal distribution scheme of an exemplary embodiment of the present invention. 100181 Figure 5 is an example of a possible phase alignment mechanism of an exemplary embodiment of the present invention. 100191 Figure 6 is a block diagram of the prior art. 100201 Figure 7 is an electrical diagram of the prior art. [00211 Figure 8 is a graph illustrating the ideal output currents profile at the fundamental frequency of the circuit of Figure 7. 100221 Figure 9 is an electrical diagram according to an emplary embodiment of the present invention shown in Figure 2.
[34] [0034] Figure 21 is another measured performance of the prior art compared to a practical implementation of an exemplary embodiment of the present invention. 100351 Figure 22 is a simulated performance of the prior art compared to a practical implementation of an exemplary embodiment of the present invention.
[36] [0036] Figure 23 is the measured performance, in terms of spectrum, of a practical implementation of an exemplary embodiment of the present invention.
[63] [0063] Figure 20 shows the measured power efficiency perfbmiance of a practical implementation of an exemplary embodiment of the Present Invention operating at the nominal design frequency where the RF power amplification block has only one peaking amplifier and where only digital phase alignment is applied.
[64] [0064] Figure 21 shows the measured power efficiency performance of the analog Doherty prior art compared to a practical implementation of an exemplary embodiment of the Present Invention (the digital Doherty transmitter of the present invention) operating at the nominal design frequency where the RE power amplification block has only one peaking amplifier and where only digital adapt power distribution was applied. [0065j Figure 22 shows the simulated power efficiency versus frequency performance of the analog Doherty prior art compared to an implementation of an exemplary embodiment of the Present invention (the digital Doherty transmitter of the present invention) where the R12 power amplification block has only one peaking amplifier and where digital adaptive power distribution and digital phase alignment was are applied.
PCT/C2013/000578 [00661 Figure 23 shows the measured performance, in terms of spectrum of a practical implementation of an exemplary embodiment of the present invention operating at the original design frequency where the RF power amplification block has only one peaking amplifier and where digital predistortion and digital adaptive power distribution are applied. 100671 As various modifications could be made to the exemplary embodiments, as described above with reference to the corresponding illustrations, without departing from the scope of the invention, it is intended that all matter contained in the foregoing description and shown in the accompanying drawings shall be interpreted as illustrative rather than limiting. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents. 18

权利要求:
Claims (1)
[1] 1. IP PEAKIV outnt ANTLIFIER21 RFoULP 1;

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US8180303B2|2008-05-28|2012-05-15|Hollinworth Fund, L.L.C.|Power amplifier architectures|CN109586677B|2017-09-29|2020-12-25|华为技术有限公司|Signal processing device, multi-input power amplification system and related method|

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CN109905092B|2017-12-11|2022-02-25|华为技术有限公司|Power amplification device and signal processing method|

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WO2019119436A1|2017-12-22|2019-06-27|华为技术有限公司|Signal processing circuit, radio frequency signal transmitter, and communication device|

法律状态:

优先权:

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US13/563,621|US8837629B2|2011-05-11|2012-07-31|Extended bandwidth digital Doherty transmitter|

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PCT/CA2013/000678|WO2014019071A1|2012-07-31|2013-07-31|Extended bandwidth digital doherty transmitter|

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